V-Class 1 Pemodelan dan Simulasi

V-Class 1 Pemodelan dan Simulasi

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1.      Perbedaan antaran static dan dynamic model adalah
Model Statis
Digunakan bila jangka waktu variabel dianggap konstan dan interelasi unsur-unsur model dinyatakan sebagai persamaan yang tidak berubah dengan waktu. Sebagian besar situasi pengambilan keputusan statis diperkirakan berulang dengan kondisi yang identik.
Contoh: satu keputusan mengenai membuat sendiri atau membeli satu produk.
Model Dinamis
Menempatkan waktu sebagai variabel bebas, sehingga model jenis ini menggambarkan dinamika suatu sistem sebagai fungsi dari waktu. Untuk memperoleh hasil, perhitungan dilakukan secara berulang-ulang (iterasi) sampai tercapai nilai kesalahan (error) yang minimal
Contoh: proyeksi rugi-laba 5 tahun dimana data input seperti biaya, harga, dan kuantitas berubah dari tahun ke tahun.
           
2.      contoh model matematika dinamis

Sebagai contoh, pertimbangkan mengikuti model matematika yang dinamis sederhana dari perekonomian nasional.dengan
C=konsumsi
I = investasi
T=pajak
G=pengeluaran pemerintah
Y=pendapatan nasional
kemudian          
C=20+0.7(Y-T)
I=2+0.1Y
T=0+0.2Y
Y=C+I+G
semua kuantitas disajikan dalam miliaran rupee


3.      kondisi agar tidak terjadi osilasi
 
V suspensi = 2.p.d/2.n/60
 
4.      Langkah-langkah dasar yang harus dilakukan saat membuat model
 
Langkah-langkah Pembuatan Model Simulasi
Untuk pembuatan model simulasi model yang dibangun harus kredibel. Representasi kredibel sistem nyata oleh model simulasi ditunjukkan oleh verifikasi dan validasi model. Verifikasi adalah proses pemeriksaan apakah logika operasional model (program komputer) sesuai dengan logika diagram alur. Kalimat sederhananya, apakah ada kesalahan dalam program? (Hoover dan Perry, 1989); verifikasi adalah pemeriksaan apakah program komputer simulasi berjalan sesuai dengan yang diinginkan, dengan pemeriksaan program komputer. Verifikasi memeriksa penerjemahan model simulasi konseptual (diagram alur dan asumsi) ke dalam bahasa pemrograman secara benar (Law dan Kelton, 1991) .

Aturan Verifikasi Dan Validasi Dalam Simulasi
Ketika membangun model simulasi sistem nyata, kita harus melewati beberapa tahapan atau level pemodelan. Pertama kita harus membangun model konseptual yang memuat elemen sistem nyata. Dari model konseptual ini kita membangun model logika yang memuat relasi logis antara elemen sistem juga variabel eksogenus yang mempengaruhi sistem. Model kedua ini sering disebut sebagai model diagram alur. Menggunakan model diagram alur ini, lalu dikembangkan program komputer, yang disebut juga sebagai model simulasi, yang akan mengeksekusi model diagram alur.

Validasi Model Konseptual
Validasi model konseptual adalah proses pembentukan abstraksi relevan sistem nyata terhadap pertanyaan model simulasi yang diharapkan akan dijawab. Validasi model simulasi dapat dibayangkan sebagai proses pengikat dimana analis simulasi, pengambil keputusan dan manajer sistem setuju aspek mana dari sistem nyata yang akan dimasukkan dalam model, dan informasi apa (output) yang diharapkan akan dihasilkan dari model. Tidak ada metode standar untuk validasi model konseptual, kita hanya akan melihat beberapa metode yang berguna untuk validasi.

 Representasi Kejadian Sistem
Metode ini menggunakan graf kejadian seperti yang digunakan dalam pengembangan model
simulasi. Teknik pembuatan grafnya juga sama. Kita harus mendefinisikan dengan jelas relasi kondisional antar kejadian. Representasi graf dapat digunakan sebagai jembatan ke model logis (model diagram alur) juga sebagai alat bantu komunikasi antara analis simulasi, pengambil keputusan dan manajer. Hampir sama dengan graf kejadian adalah model diagram alur, merepresentasikan aliran entitas melalui sistem.

Identifikasi Eksplisit Elemen yang Harus Ada dalam Model
Pada umunya model konseptual tidak dapat memasukkan semua detil sistem nyata, melainkan hanya elemen yang relevan dengan pertanyaan yang diharapkan akan dijawab. Dalam pembuatan model konseptual, semua kejadian, fasilitas, peralatan, aturan operasi, variabel status, variabel keputusan dan ukuran kinerja harus jelas diidentifikasikan dan akan menjadi bagian dari model simulasi. Kita juga harus mengidentifikasikan dengan jelas semua elemen yang tidak akan dimasukkan dalam model simulasi. Analis simulasi, pengambil keputusan dan manajer harus bergabung untuk memutuskan berapa banyak sistem nyata harus dimasukkan untuk menghasilkan representasi valid sistem nyata.

Verifikasi dan Validasi Model Logis
Bentuk model logis tergantung dari bahasa pemrograman yang akan digunakan. Jika model konseptual sudah dibangun dengan baik, verifikasi model konseptual bukan pekerjaan kompleks. Ada beberapa pertanyaan yang harus dijawab sebelum kita yakin bahwa model logis merepresentasikan model konseptual. Salah satu pendekatan yang digunakan untuk verifikasi model logis adalah dengan fokus pada:
1. apakah kejadian dalam model diproses dengan benar?
2. apakah rumus matematika dan relasi dalam model valid?
3. apakah statistik dan ukuran kinerja diukur dengan benar?

Verifikasi Statistik dan Ukuran Kinerja
Kesalahan umum yang terjadi dalam pemodelan simulasi adalah gagal memperbaharui statistik relevan dan ukuran kinerja secara tepat ketika suatu kejadian terjadi. Salah satu cara yang dapat digunakan untuk verifikasi bahwa statistik dan ukuran kinerja diperbaharui dengan benar adalah menggunakan graf kejadian. Dalam kebanyakan bahasa simulasi, beberapa tipe ukuran statistik dapat dikumpulkan secara otomatis saat simulasi dieksekusi. Oleh karena itu, ukuran statistik dibangun dalam metode yang transparan ke analis, sehingga mengurangi kesempatan kesalahan statistik.

Verifikasi Model Komputer
Model komputer diverifikasi dengan menunjukkan bahwa program komputer adalah implementasi tepat model logis. Beberapa metode yang digunakan untuk verifikasi model komputer adalah unik terhadap simulasi, sementara metode verifikasi lain sama dengan yang digunakan dalam setiap pengembangan perangkat lunak lainnya. Verifikasi model komputer sangat tergantung dengan bahasa pemrograman yang digunakan dan tidak ada metodologi umum yang disetujui. Verifikasi model komputer sering membutuhkan imaginasi dan keahlian tinggi analis, dan ini adalah satu aktivitas dalam proyek simulasi yang dilakukan tanpa bantuan pengambil keputusan dan manajer.

Penelusuran Simulasi
Beberapa bahasa simulasi menyediakan kemampuan-terpasang penelusuran simulasi sebagaimana terjadinya. Ketika model simulasi diprogram menggunakan bahasa umum, tentu saja analis harus membangun kemampuan penelusuran dalam kode program. Ketika membangun memprogram model logika, mekanisme penelusuran simulasi harus dimasukkan sebagai bagian dari disain program dan tidak ditutupi ketika ada kesalahan dalam program komputer.

Pengujian Relasi Logis
Relasi ini dapat didasarkan pada hukum konservasi atau secara statistik. Jika relasi ini tidak diperhatikan, maka program bukan implementasi benar dari model logis. Titik paling sesuai untuk memeriksa relasi itu adalah ketika model berjalan tahap demi tahap. Secara tipikal, kesalahan pemrograman tidak acak dan berdistribusi secara uniform, tetapi berkumpul secara kluster.

Validasi Model Simulasi
1. Eksperimen dengan model simulasi untuk eksperimen sistem aktual
2. Kemudahan atau kesulitan dari proses validasi tergantung pada kompleksitas sistem yang dimodelkan
3. Sebuah model simulasi dari sebuah sistem yang kompleks hanya dapat menjadi pendekatan terhadap aktual system

Perbandingan Output Simulasi dengan Sistem Nyata
Membandingkan output ukuran kinerja model simulasi dengan ukuran kinerja yang sesuai dari sistem nyata adalah metode yang paling sesuai untuk melakukan validasi model simulasi. Jika ukuran kinerja sistem nyata cukup tersedia, uji statistik umum seperti uji t digunakan dimana kita menguji hipotesis kesamaan nilai rata-rata. Kadang-kadang uji F juga dapat digunakan untuk menguji kesamaan ragam sistem nyata dengan model simulasi. Beberapa metode nonparametrik lainnya juga bisa digunakan, misalnya ChiSquare dan Kolmogorov Smirnov.

Metode Delphi
Metode Delphi dikembangkan sebagai pendekatan ke analisis permasalahan ketika sangat sedikit data tersedia atau sistem nyata sedang dipertimbangkan. Dalam metode Delphi, sekelompok ahli terpilih membentuk panel yang akan menghasilkan jawaban konsensus terhadap pertanyaan yang diajukan ke mereka. Dalam lingkungan simulasi, panel mungkin terdiri dari manager dan pengguna sistem yang sedang dimodekan dan pertanyaan adalah tentang perilaku atau kinerja sistem di bawah kondisi operasi tertentu. Metode Delphi tidak memasukkan diskusi tatap muka, oleh karena itu terhindar dari ketegangan diskusi kelompok seperti dominasi peserta paling vokal. Metode dikembangkan oleh perusahaan RAND dan telah digunakan dalam berbagai bentuk.

Pengujian Turing
Metode ini diajukan oleh Alan Turing sebagai uji intelegensia buatan. Seorang ahli atau panel ahli menyediakan ringkasan gambaran atau laporan berdasarkan sistem nyata dan model simulasi. Jika ahli tidak dapat mengidentifikasi laporan berdasarkan output model simulasi, kredibilitas model ditingkatkan. Kesulitan utama validasi model menggunakan uji Turing adalah penyesuaian ukuran kinerja sistem nyata sehingga pengaruh tidak dimaksudkan sebagai bagian dari model simulasi dihilangkan.


 

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